Field of the Invention: The present invention relates generally to stereolithography and, more specifically, to the use of stereolithography to fabricate structures on, or components of, semiconductor testing apparatus and to the resulting structures.
State of the Art: In the past decade, a manufacturing technique termed “stereolithography,” also known as “layered manufacturing,” has evolved to a degree where it is employed in many industries.
Essentially, stereolithography, as conventionally practiced, involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or “sliced” into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object. Surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries. This is followed by selective consolidation or fixation of the material to at least a semisolid state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer. The unconsolidated material employed to build an object may be supplied in particulate or liquid form and the material itself may be consolidated, fixed or cured, or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size. When a liquid is employed, resolution is highly dependent upon the minimum surface area of the liquid which can be fixed (cured) and the minimum thickness of a layer which can be generated given the viscosity of the liquid and other parameters, such as transparency to radiation or particle bombardment (see below) used to effect at least a partial cure of the liquid to a structurally stable state. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end, and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
An early application of stereolithography enabled rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed could be rapidly generated. Prototypes of objects could be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production.
In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials, and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques.
However, to the inventor's knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products including other pre-existing components in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results are required.
In the electronics industry, computer chips are typically manufactured by configuring a large number of integrated circuits on a wafer and subdividing the wafer to form singulated devices or dice. Such dice, including so-called “flip-chip” dice, have “solder bumps” or other conductors, or conductive structures, for electrically connecting each die to circuitry external thereto. These conductors are also useful for temporary connection of a die to a test circuit to determine its fitness for the intended use. Tests may be conducted before or after the die has been packaged.
One type of conventional test apparatus that is used to test the electrical characteristics of semiconductor devices includes a carrier substrate, a test substrate positioned on the carrier substrate, and a fence disposed over the test substrate. The carrier substrate includes terminals and electrical traces that lead from the terminals to communicate with test equipment. Terminals of the carrier substrate are wire bonded to contact pads on the test substrate. The contact pads of the test substrate communicate with test pads thereof. The test pads are arranged to correspond to a pattern of conductors, such as solder balls, conductive pillars, bond pads, or other conductive structures of a semiconductor device to be tested. The fence forms an aperture over the test substrate to facilitate alignment of the semiconductor device to be tested relative to the substrate. As a die to be tested is aligned with a test substrate, test pads of the test substrate temporarily mate or contact the conductors of the semiconductor device. Such test apparatus can be configured to test bare or minimally packaged semiconductor dice or packaged semiconductor devices, such as ball grid array (BGA) packages and chip-scale packages (CSPs).
Conventionally, the bond wires of a test apparatus have been covered with a silicone gel or a nonconductive epoxy “glob-top” material. As such materials can flow, the use of such materials typically also requires that external fences or walls be used to contain such materials in the desired locations. Internal fences or walls may also be required to prevent such glob top, silicone, and other materials from flowing onto the test pads of a test substrate, which can prevent the electrical connection of tested semiconductor devices to the test substrate. Otherwise, if flowable materials are used to cover wire bonds, these materials may have to be removed from the test pads or from the conductors of the tested semiconductor device to ensure adequate electrical connections between the test substrate and the semiconductor device assembled therewith.
In other test apparatus, a photoresist material is used to cover the bond wires that connect a test substrate to a carrier substrate. When photoresist materials are used to protect bond wires, the use of a mask and several exposure and developing steps are required.
Accordingly, there is a need for a method of efficiently and effectively protecting the bond wires of semiconductor device test apparatus, as well as protective structures and test apparatus formed by such a method.